China Chips Cost More Without EUV

Chinese chipmakers are absorbing higher costs to produce advanced silicon without access to extreme ultraviolet lithography tools. Experts say the reliance on older deep ultraviolet equipment forces manufacturers to split complex layers into multiple simpler patterns. This multi-step process increases the time required for production and raises the likelihood of defects. Consequently, the bill for each wafer grows larger with every additional exposure step.

Export controls have kept ASML's EUV machines out of China. These tools use 13.5 nanometer wavelength light to print fine features on processors. Analysts estimate the gap in EUV capability between China and the West is at least five years. Despite this restriction, domestic manufacturers have made progress. A 2023 teardown of the Huawei Mate 60 Pro showed the Kirin 9000S processor was made by SMIC using a 7 nanometer class process without EUV. Recent analysis suggests SMIC has moved closer to 5 nanometer density with its current DUV-based process.

Chris Mack, co-founder and CTO of Fractilia, notes that industry standards previously held that three exposures on a 193 immersion tool cost about the same as one EUV exposure. However, at four masks, EUV becomes the more economical choice. The added steps introduce alignment challenges. Each new pattern must align precisely with previous etching. More exposures lead to accumulated overlay errors and process variation. Designers often add space around features to compensate, which enlarges the chip and reduces the number of dies per wafer. Mack states, 'You don't sell wafers, you sell die.'

Memory production illustrates the efficiency gap. A June report from Morgan Stanley estimated that CXMT produces only about one-third as many bits per wafer as Western rivals. The bank labeled lithography access a hard ceiling for Chinese memory development. Mack cautions that node labels like 5 nanometer or 3 nanometer have limited meaning without context. He notes SMIC's N+3 process is less scaled than established 5 nanometer processes from Samsung and TSMC.

DUV technology still has potential. Micron developed its 1-alpha DRAM without EUV using multiple patterning and tight process control. Mack said Micron pushed 193 immersion technology farther than other memory makers. Morgan Stanley believes CXMT can achieve 1-alpha DRAM for HBM3e without EUV. Douglas Fuller from Copenhagen Business School expects advanced packaging to allow DUV use for latest DRAM generations by the end of the decade. Mack added that China could advance significantly if it had the full 193 immersion ecosystem and designed products around it, though he stressed memory is easier to manufacture than logic.

EUV has its own drawbacks, including stochastic effects that require higher exposure doses and greater cost. Nevertheless, Mack said he would be hard pressed to believe a 3 nanometer or 2 nanometer node could be economically viable without EUV. Micron eventually turned to EUV for its 1-gamma DRAM. This generation delivers more than 30% greater bit density per wafer than the previous 1-beta generation.

Chinese chipmakers are not expected to stall. They can continue pushing DUV while accepting larger dies, poorer yields, or longer manufacturing times. They can also add capacity. Morgan Stanley assumes CXMT will stay on 1-alpha without EUV but will lift its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 through new greenfield capacity. The bank also expects China's AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030. EUV, HBM, and advanced software are expected to leave a persistent gap in that timeframe.